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control is passed at the end of the interrupt handler. CSRR0, shown in

Table 25, holds the

address of the instruction where the interrupted process should resume. The instruction is

interrupt-specific; for details, see

Chapter 6: Interrupts and exceptions.” When rfci executes,

instruction execution continues at the address in CSRR0. CSRR0 and CSRR1 are not

affected by rfi or rfdi.

Critical save/restore register 1 (CSRR1)

CSRR1, shown in

Table 26, is used to save and restore machine state during critical

interrupts. MSR contents are placed into CSRR1. When rfci executes, the contents of

CSRR1 are restored into MSR. CSRR1 bits that correspond to reserved MSR bits are also

reserved. (See

Chapter 4.4.1: Machine state register (MSR) on page 43.”) CSRR0 and

CSRR1 are not affected by rfi or rfdi. Reserved MSR bits can be altered by rfi, rfci, or rfdi.

Data exception address register (DEAR)

DEAR, shown in

Table 27, is loaded with the effective address of a data access (caused by

a load, store, or cache management instruction) that results in an alignment, data TLB miss,

or data storage interrupt.

Interrupt vector prefix register (IVPR)

The IVPR, shown in <Cross Refs>Figure 28, is used during interrupt processing to

determine the starting address for the software interrupt handler. The value contained in the

vector offset field of the IVOR selected for a particular interrupt type is concatenated with the

value in the IVPR to form an instruction address from which execution is to begin.

Table 25.

Critical save/restore register 0 (CSRR0)

Field

Next instruction address

Reset

Undefined on

m_por assertion, unchanged on p_reset_b assertion

R/W

SPR

SPR 58

Table 26.

Critical save/restore register 1 (CSRR1)

Field

MSR state information

Reset

Undefined on

m_por assertion, unchanged on p_reset_b assertion

R/W

SPR

SPR 59

Table 27.

Data exception address register (DEAR)

Field

Exception address

Reset

Undefined on

m_por assertion, unchanged on p_reset_b assertion

R/W

SPR

SPR 61

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