UM0434 datasheet(34/390 Pages) STMICROELECTRONICS

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UM0434

e200z3 core complex overview

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3.6.5

System bus (core complex interface) features

The features of the core complex interface are as follows:

●

Independent instruction and data buses

●

Advanced microcontroller bus architecture (AMBA) and advanced high-performance

bus (AHB2.v6)-Lite protocol

●

32-bit address bus plus attributes and control on each bus

●

Instruction interface has 64-bit read data bus

●

Data interface has separate unidirectional 64-bit read data bus and 64-bit write data

bus

●

Pipelined, in-order accesses for both buses.

3.6.6

Nexus3 module features

The Nexus3 module provides real-time development capabilities for e200z3 processors in

compliance with the IEEE-ISTO Nexus 5001-2003 standard. This module provides

development support capabilities without requiring the use of address and data pins for

internal visibility.

A portion of the pin interface (the JTAG port) is shared with the OnCE/Nexus1 unit. The

IEEE-ISTO 5001-2003 standard defines an extensible auxiliary port, which is used in

conjunction with the JTAG port in e200z3 processors.

3.7

Legacy support of PowerPC architecture

This section provides an overview of the architectural differences and compatibilities of the

e200z3 core compared with the AIM PowerPC architecture. The two levels of the e200z3

core programming environment are as follows:

●

User level—This defines the base user-level instruction set, registers, data types,

memory conventions, and the memory and programming models seen by application

programmers.

●

Supervisor level—This defines supervisor-level resources typically required by an

operating system, the memory management model, supervisor-level registers, and the

exception model.

In general, the e200z3 core supports the user-level architecture from the classic PowerPC

architecture. The following sections are intended to highlight the main differences. For

specific implementation details refer to the relevant chapter.

3.7.1

Instruction set compatibility

The following sections describe the user and supervisor instruction sets.

User instruction set

The e200z3 core executes legacy user-mode binaries and object files except for the

following:

●

The e200z3 core supports vector and scalar single-precision floating-point operations

as APUs. These instructions have different encoding than the AIM definition of the

PowerPC architecture. Additionally, the e200z3 core uses GPRs for floating-point

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