UM0434 datasheet(92/390 Pages) STMICROELECTRONICS

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UM0434

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The MAS2 register is shown in

Table 77.

MAS2 fields are defined in

Table 78.

Table 76.

MAS1 - descriptor context and configuration control

Bits

Name

Description

VALID

TLB entry valid.

0 This TLB entry is invalid.

1 This TLB entry is valid.

IPROT

Invalidation protect. Protects TLB entry from invalidation by tlbivax (TLB1 only), or flash

invalidates through MMUCSR0[TLB1_FI].

0 Entry is not protected from invalidation.

1 Entry is protected from invalidation as described in

Chapter 7.3.1: IPROT

invalidation protection in TLB1 on page 198.”

34–39

—

Reserved, should be cleared.

40–47

TID

Translation ID. Compared with the current process IDs of the effective address to be translated.

A TID value of 0 defines an entry as global and matches with all process IDs.

48–50

—

Reserved, should be cleared.

Translation address space. Compared with MSR[IS] or MSR[DS] (depending on the type of

access) to determine if this TLB entry may be used for translation.

52–55

TSIZE

Entry page size.

Supported page sizes are:

0001 4 Kbytes 0110 4 Mbytes.

0010 16 Kbytes 0111 16 Mbytes.

0011 64 Kbytes 1000 64 Mbytes.

0100 256 Kbytes 1001 256 Mbytes.

0101 1 Mbyte.

All other values are undefined.

56–63

—

Reserved, should be cleared.

Table 77.

MMU assist register 2 (MAS2)

SPR

626

Access: Supervisor read/write

EPN

Reset

Undefined

51 52

54 55 56 57 58 59 60 61 62 63

EPN

—VLE W

M G E

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