UM0434 datasheet(84/390 Pages) STMICROELECTRONICS

84 / 390 page

UM0434

85/391

Table 60.

HID0 field descriptions

Bits

Name

Description

EMCP

Enable machine check signal (

p_mcp_b). Used to mask out further machine check

exceptions caused by assertion of

p_mcp_b.

p_mcp_b is disabled.

p_mcp_b is enabled. If MSR[ME] = 0, asserting p_mcp_b causes checkstop. If

MSR[ME] = 1, asserting

p_mcp_b causes a machine check interrupt.

33–37

—

Reserved, should be cleared.

38–39

BPRED

Branch prediction (acceleration) control. Controls BTB lookahead for branch acceleration.

Note that for branches with AA = 1, the msb of the displacement field is still used to indicate

forward/backward, even though the branch is absolute. Used in conjunction with BUCSR.

00 Branch acceleration is enabled.

01 Branch acceleration is disabled for backward branches.

10 Branch acceleration is disabled for forward branches.

11 Branch acceleration is disabled for both branch directions.

DOZE

Doze power management mode. Doze mode is invoked by setting MSR[WE] while DOZE = 1.

0 Doze mode is disabled.

1 Doze mode is enabled.

NAP

Nap power management mode. Nap mode is invoked by setting MSR[WE] while NAP=1.

0 Nap mode is disabled.

1 Nap mode is enabled.

SLEEP

Sleep power management mode. Sleep mode is invoked by setting MSR[WE] while WE=1.

Only one of DOZE, NAP, or SLEEP should be set for proper operation.

0 Sleep mode is disabled.

1 Sleep mode is enabled.

43–45

—

Reserved, should be cleared.

ICR

Interrupt inputs clear reservation.

0 External and critical input interrupts do not affect reservation status.

1 External and critical input interrupts clear an outstanding reservation.

NHR

Not hardware reset. Provided for software use. Set anytime by software, cleared by reset.

0 Indicates a reset to a reset exception handler if software has previously set this bit.

1 Indicates to a reset exception handler that there was no reset if software has previously set

this bit.

—

Reserved, should be cleared.

TBEN

Time base enable. Used to enable the time base and decrementer.

0 Time base is disabled.

1 Time base is enabled.

SEL_TBCL

Select time base clock. Selects the time base clock source. This bit must altered while the

time base is disabled to prevent counter glitches. Timer interrupts should be disabled

beforehand, and TBL and TBU are reinitialized after a change of time base clock source.

0 Time base is based on processor clock.

1 Time base is based on the

p_tbclk input.

UM0434 Datasheet(PDF) 84 Page - STMicroelectronics

UM0434 Datasheet(HTML) 84 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL