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UM0434 Datasheet(PDF) 71 Page - STMicroelectronics

Part # UM0434
Description  The primary objective of this user?셲 manual is to describe
PDF  390 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UM0434 Datasheet(HTML) 71 Page - STMicroelectronics

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Register model
UM0434
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Table 51.
DBCR0 field descriptions
Bits
Name
Description
32
EDM
External debug mode. For software, this bit is read-only. Software can use EDM to determine
whether external debug has control over debug registers. The hardware debugger must set EDM
before other DBCR0 bits (and other debug registers) can be altered. On the initial setting of EDM,
all other bits are unchanged. EDM is writable only through the OnCE port.
0External debug mode is disabled. Internal debug events not mapped into external debug events.
1External debug mode is enabled. Events do not cause the CPU to vector to interrupt code.
Software is not permitted to write to debug registers (DBCR0
–DBCR3, DBSR, DBCNT, IAC1–
IAC4, DAC1–DAC2).
Note: DBSR status bits should be cleared before external debug mode is disabled to avoid
internal imprecise debug interrupts.
33
IDM
Internal debug mode.
0 Debug exceptions are disabled. Debug events do not affect DBSR.
1 Debug exceptions are enabled. Enabled debug events update the DBSR. If MSR[DE] = 1, a
debug event or the recording of an earlier debug event in the DBSR when MSR[DE] was cleared
causes a debug interrupt.
34–35
RST
Reset control.
00 No function.
01 Reserved.
10
p_resetout_b set by debug reset control. Allows external device to initiate processor reset.
11 Reserved.
36
ICMP
Instruction complete debug event enable.
0 ICMP debug events are disabled.
1 ICMP debug events are enabled.
37
BRT
Branch taken debug event enable.
0 BRT debug events are disabled.
1 BRT debug events are enabled.
38
IRPT
Interrupt taken debug event enable.
0 IRPT debug events are disabled.
1 IRPT debug events are enabled.
39
TRAP
Trap taken debug event enable.
0 TRAP debug events are disabled.
1 TRAP debug events are enabled.
40
IAC1
Instruction address compare 1 debug event enable.
0 IAC1 debug events are disabled.
1 IAC1 debug events are enabled.
41
IAC2
Instruction address compare 2 debug event enable.
0 IAC2 debug events are disabled.
1 IAC2 debug events are enabled.
42
IAC3
Instruction address compare 3 debug event enable.
0 IAC3 debug events are disabled.
1 IAC3 debug events are enabled.



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