UM0434 datasheet(70/390 Pages) STMICROELECTRONICS

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UM0434

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Refer to

Section : Debug control register 3 (DBCR3) on page 77,” for details on updates to

the DBCNT register. There are restrictions on how the DBCNT and DBCR3 register are

modified when one or more counters are enabled.

4.12.3

Debug control and status registers (DBCR0–DBCR3)

DBCR0–DBCR3 enable debug events, reset the processor, control timer operation during

debug events and set the debug mode of the processor. The debug status register (DBSR)

records debug exceptions while internal or external debug mode is enabled.

To ensure that any alterations enabling/disabling debug events are effective, the e200z3

requires that a context synchronizing instruction follow an mtspr that updates a DBCR or

DBSR. The context synchronizing instruction may or may not be affected by the alteration.

Typically, an isync is used to create a synchronization boundary beyond which it can be

guaranteed that the newly written control values are in effect. For watchpoint generation and

counter operation, configuration settings in DBCR1–DBCR3 are used, even though the

corresponding events can be disabled (via DBCR0) from setting DBSR flags.

Debug Control Register 0 (DBCR0)

DBCR0 is used to enable debug modes and controls which debug events are allowed to set

DBSR flags. The e200z3 adds bits to this register, as shown in

Table 50.

Table 51 provides field definitions for DBCR0.

Table 50.

DBCR0 Register

33 34 35

44 45 46 47

Field EDM IDM RST ICMP

BRT

IRPT

TRAP

IAC1

IAC2

IAC3 IAC4 DAC1 DAC2

Reset

All zeros(1)

DBCR0[EDM] is affected by

j_trst_b or m_por assertion, and while in the test_logic_reset state, but not by

p_reset_b. All other bits are reset by processor reset p_reset_b as well as by m_por.

R/W

62 63

RET

—

DEVT1 DEVT2 DCNT1 DCNT2 CIRPT CRET VLES

—

Reset

All zeros 1

R/W

SPR

SPR 308

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