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UM0434 Datasheet(PDF) 36 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 36 Page - STMicroelectronics |
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36 / 390 page  UM0434 e200z3 core complex overview 37/391 3.7.5 Reset Book E–compliant cores do not share a common reset vector with the AIM version of the PowerPC architecture. Instead, at reset, fetching begins at address 0xFFFF_FFFC. In addition to the Book E reset definition, the EIS and e200z3 core define specific aspects of the MMU page translation and protection mechanisms. Unlike the AIM version of the PowerPC core, as soon as instruction fetching begins, the e200z3 core is in virtual mode with a hardware-initialized TLB entry. 3.7.6 Little-endian mode Unlike the AIM version of the PowerPC architecture, where little-endian mode is controlled on a system basis, Book E allows control of byte ordering on a memory-page basis. In addition, the little-endian mode used in Book E is true little-endian byte ordering (byte invariance). |
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