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UM0434 Datasheet(PDF) 68 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 68 Page - STMicroelectronics |
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68 / 390 page ![]() UM0434 Register model 69/391 4.11.5 Decrementer auto-reload register (DECAR) If the auto-reload function is enabled (TCR[ARE] = 1), the auto-reload value in DECAR, shown in Table 46, is written to DEC when DEC decrements from 0x0000_0001 to 0x0000_0000. Writing DEC with zeros by using an mtspr does not automatically generate a decrementer interrupt. 4.12 Debug registers This section describes software-accessible debug registers for use by special debug tools and debug software, not by general application code. Software access to these registers is conditioned by the external debug mode control bit (DBCR0[EDM]), which can be set by the hardware debug port. If DBCR0[EDM] is set, software is prevented from modifying debug register values. Execution of an mtspr instruction targeting a debug register does not cause modifications to occur. In addition, since the external debugger hardware may be manipulating debug register values, the state of these registers is not guaranteed to be consistent if read by software with an mfspr instruction other than DBCR0[EDM]. 4.12.1 Debug address and value registers Instruction address compare registers IAC1–IAC4 hold instruction addresses for comparison. In addition, IAC2 and IAC4 hold mask information for IAC1 and IAC3, respectively, when address bit match compare modes are selected. Note: During instruction address comparisons, the low-order two address bits of the instruction address and the corresponding IAC register are ignored. Data address compare registers DAC1 and DAC2 hold data access addresses for comparison. In addition, DAC2 holds mask information for DAC1 when address bit match compare mode is selected. Instruction address compare registers (IAC1–IAC4) IAC1–IAC4, shown in Table 47, hold instruction addresses for comparison. Table 46. Decrementer auto-reload register (DECAR) 32 63 Field Decrementer auto-reload value Reset Undefined on m_por assertion, unchanged on p_reset_b assertion R/W R/W SPR SPR 54 Table 47. Instruction address compare registers (IAC1–IAC4) 32 616263 Field Instruction address — Reset All zeros R/W R/W SPR SPR 312 (IAC1); SPR 313 (IAC2); SPR 314 (IAC3); SPR 315 (IAC4) |
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