UM0434 datasheet(49/390 Pages) STMICROELECTRONICS

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Note that CR0 may not reflect the true (infinitely precise) result if overflow occurs. For further

details, refer to the

EREF.

CR setting for store conditional instructions

CR0 is also set by the integer store conditional instruction, stwcx.. See instruction

descriptions in

Chapter 5: Instruction model,” for details on how CR0 is set.

CR setting for compare instructions

For compare instructions, a CR field specified by the BI field in the instruction is set to reflect

the result of the comparison, as shown in

Table 18.

A complete description of how the bits are set is given in the

EREF.

Table 17.

CR0 field descriptions

Bit

Name

Description

Negative (LT)

Bit 32 of the result is equal to 1.

Positive (GT)

Bit 32 of the result is equal to 0 and at least one of bits 33–63 of the result is non-

zero.

Zero (EQ)

Bits 32–63 of the result are equal to 0.

Summary overflow (SO) This is a copy of the final state of XER[SO] at the completion of the instruction.

Table 18.

CR setting for compare instructions

Bit

Bit Expression

CR Bits

Description

Book E

0–2

3–4

n[0]

4 * cr0 + lt (or lt)

4 * cr1 + lt

4 * cr2 + lt

4 * cr3 + lt

4 * cr4 + lt

4 * cr5 + lt

4 * cr6 + lt

4 * cr7 + lt

000

001

010

011

100

101

110

111

Less than (LT).

For integer compare instructions:

rA < SIMM or rB (signed comparison) or rA

< UIMM or rB (unsigned comparison).

n[1]

4 * cr0 + gt (or gt)

4 * cr1 + gt

4 * cr2 + gt

4 * cr3 + gt

4 * cr4 + gt

4 * cr5 + gt

4 * cr6 + gt

4 * cr7 + gt

000

001

010

011

100

101

110

111

Greater than (GT).

For integer compare instructions:

rA > SIMM or rB (signed comparison) or rA

> UIMM or rB (unsigned comparison).

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