UM0434 datasheet(88/390 Pages) STMICROELECTRONICS

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UM0434

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4.16.2

MMU configuration register (MMUCFG)

The MMU configuration register (MMUCFG) is a 32-bit read-only register. The SPR number

for MMUCFG is 1015 in decimal. MMUCFG, which provides information about the

configuration of the e200z3 MMU design, is shown in

Table 67.

The MMUCFG fields are described in

Table 68.

Table 66.

MMUCSR0 field descriptions

Bits

Name

Description

32–61

—

Reserved, should be cleared.

TLB1_FI

TLB1 flash invalidate

0 No flash invalidate

1 TLB1 invalidation operation. Hardware initiates a TLB1 invalidation,

after which TLB1_FI is cleared. Setting TLB1_FI while an invalidation

operation is in progress causes an undefined operation. Clearing

TLB1_FI while an invalidation operation is in progress is ignored. TLB1

invalidation operations require 3 cycles to complete.

—

Reserved, should be cleared.

Table 67.

MMU configuration register 1 (MMUCFG)

52 53

57 58 59

Field

—

NPIDS

PIDSIZE

—

NTLBS

MAVN

Reset

0000_0000_0000_0000_0

000_1

001_11

R/W

Read only

SPR

SPR 1015

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