UM0434 datasheet(83/390 Pages) STMICROELECTRONICS

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UM0434

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4.13

Hardware implementation dependent registers

Hardware implementation-dependent registers 0 and 1 (HID0 and HID1) are configuration

registers to control various processor and system functions.

4.13.1

Hardware implementation dependent register 0 (HID0)

HID0, shown in

Table 59, is used for various configuration and control functions.

HID0 fields are described in

Table 60.

DAC2W

Data address compare 2 write debug event. Set if a write-type DAC2 debug event occurs while

DBCR0[DAC2] = 0b01 or DBCR0[DAC2] = 0b11.

RET

Return debug event. Set if a Return debug event occurs.

49–52

—

Reserved, should be cleared.

DEVT1

External debug event 1 debug event. Set if a DEVT1 debug event occurs.

DEVT2

External debug event 2 debug event. Set if a DEVT2 debug event occurs.

DCNT1

Debug counter 1 debug event. Set if a DCNT1 debug event occurs.

DCNT2

Debug counter 2 debug event. Set if a DCNT2 debug event occurs.

CIRPT

Critical interrupt taken debug event. Set if a critical interrupt taken debug event occurs.

CRET

Critical return debug event. Set if a critical return debug event occurs.

59–62

—

Reserved, should be cleared.

CNT1TRG Counter 1 triggered. Set if debug counter 1 is triggered by a trigger event.

Table 58.

DBSR field descriptions (continued)

Bits

Name

Description

Table 59.

Hardware implementation dependent register 0 (HID0)

43 45 46

Field EMCP

—

BPRED

DOZE NAP SLEEP — ICR NHR

Reset

All zeros

R/W

—

TBENSEL_TBCLKDCLREE DCLRCECICLRDEMCCLRDE DAPUEN

—

Reset

All zeros

R/W

SPR

SPR 1008

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