UM0434 datasheet(77/390 Pages) STMICROELECTRONICS

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UM0434

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Note:

If the counters operate independently, both may count for the same instruction.

The debug counter register (DBCNT) is configured by DBCR3[CONFIG] to operate either as

separate 16-bit counter 1 and counter 2 or as a combined 32-bit counter (using control bits

in DBCR3 for counter 1). Counters are enabled when any of their respective count enable

event control bits are set and either DBCR0 or DBCR0[EDM] is set. Counter 1 can be

configured to count down on a number of different debug events. Counter 2 is also

configurable to count down on instruction complete, instruction or data address compare

events, and external events.

Special capability is provided for counter 1 to be triggered to begin counting down by a

subset of events (IAC1, IAC3, DAC1R, DAC1W, DEVT1, DEVT2, and counter 2). When one

or more of the counter 1 trigger bits is set (IAC1T1, IAC3T1, DAC1RT1, DAC1WT1,

DEVT1T1, DEVT2T1, CNT2T1), counter 1 is frozen until at least one of the triggering events

occurs and is then enabled to begin operation. Triggering status for counter 1 is provided in

the debug status register. Triggering mode is enabled by an mtspr DBCR3 which sets one

or more of the trigger enable bits and also enables counter 1. The trigger can be re-armed

by clearing the DBSR[CNT1TRG] status bit.

Most combinations of enables do not make sense and should be avoided. For example, if

DBCR3[ICMP] is set for counter 1, no other count enable should be set for counter 1.

Conversely, multiple instruction address compare count enables are allowed to be set and

can be useful.

Due to instruction pipelining issues and other constraints, most combinations of events are

not supported for event counting. Only the following combinations are for use; other

combinations are not supported:

●

Any combination of IAC[1–4]

●

Any combination of DAC[1–2] including linking

●

Any combination of DEVT[1–2]

●

Any combination of IRPT and RET

Limited support is provided for any combination of IAC[1–4] with DAC[1–2] (linked or

unlinked).

Due to pipelining and detection of IAC events early in the pipeline and DAC events late in the

pipeline, no guarantee is made on the exact instruction boundary that a debug exception is

generated when IAC and DAC events are combined for counting. This also applies when

counter 1 is triggered by counter 2, and a combination of IAC and DAC events is enabled for

the counters, even if only one of these types is enabled for a particular counter. In general,

when an IAC event logically follows a DAC event within several instructions, it cannot be

recognized immediately because the DAC event may not be generated in the pipeline at the

time the IAC appears. Thus, the counter may not decrement to zero for the IAC event until

after the instruction with the IAC (and perhaps several additional instructions) proceeds

down the execution pipeline. The instruction boundary where the debug exception is

actually generated typically follows the IAC by up to several instructions.

Note that the counters operate regardless of whether counters are enabled to generate

debug exceptions.

If counter 2 is used to trigger counter 1, counter 2 events should not normally be enabled in

DBCR0 and are not blocked.

Note:

Multiple IAC or DAC events are not counted during an lmw or stmw instruction, and no

count occurs if either is interrupted by a critical input or external input interrupt before

completion.

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