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UM0434 Datasheet(PDF) 38 Page - STMicroelectronics |
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UM0434 Datasheet(HTML) 38 Page - STMicroelectronics |
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38 / 390 page  UM0434 Register model 39/391 Figure 3. e200z3 Programmer’s model 6. The 64-bit registers are accessed by the SPE as separate 32-bit registers by SPE instructions. Only SPE vector instructions can access the upper word. 7. USPRG0 is a separate physical register from SPRG0. 8. EIS specific registers not part of the Book E architecture. 9. IVOR9 (handles auxiliary processor unavailable interupt) is defined by the EIS but not supported by the e200z3. 10. e200z3 specific registers may not be supported by other PowerPC processors. 4.1 PowerPC Book E registers The e200z3 supports most of the registers defined by Book E architecture. Notable exceptions are the floating-point registers FPR0–FPR31 and the FPSCR. The e200z3 does not support the Book E floating-point architecture in hardware. The GPRs are extended to 64 bits. The Book E registers in the e200z3 are as follows: User-Level Registers General-Purpose Registers Instruction on-Accessible Registers User General SPR (Read/Write) 0 31 32 63 0 31 32 63 32 63 User SPR general 0 (upper) GPR01 (lower) General- purpose registers CR Condition register spr 256 USPRG02 GPR1 spr 9 CTR Count register General SPRs (Read-Only) GPR2 ···· spr 8 LR Link register spr 260 SPRG4 SPR general registers 4–7 GPR31 spr 261 SPRG5 spr 1 XER Integer exception register spr 262 SPRG6 L1 Cache (Read-Only) spr 512 SPEFSCR3 SP/embedded FP status/control register spr 263 SPRG7 L1 cache configuration register 0 spr 515 L1CFG03 ACC3 Accumulator Time-Base Registers (Read-Only) spr 268 TBL Time base lower/upper spr 269 TBU Supervisor-Level Registers Interrupt Registers Configuration Registers 32 63 32 63 32 63 spr 63 IVPR Interrupt vector prefix register spr 400 IVOR0 Interrupt vector offset registers 0–154 MSR Machine state register spr 401 IVOR1 ···· spr 26 SRR0 Save/restore registers 0/1 spr 1023 SVR3 System version register spr 27 SRR1 spr 415 IVOR15 spr 286 PIR Processor ID register spr 58 CSRR0 Critical SRR 0/1 Processor version register spr 528 IVOR323 Interrupt vector offset registers 32–34 spr 287 PVR spr 59 CSRR1 spr 529 IVOR333 spr 574 DSRR03 Debug interrupt SRR 0/1 spr 530 IVOR343 Timer/Decrementer Registers spr 575 DSRR13 Exception syndrome register spr 22 DEC Decrementer spr 62 ESR MMU Control and Status (Read/Write) Decrementer auto-reload register MMU control and status register 0 spr 54 DECAR spr 572 MCSR3 Machine check syndrome register spr 1012 MMUCSR03 spr 284 TBL Time base lower/upper spr 61 DEAR Data exception address register spr 624 MAS03 MMU assist registers 0–4 and 6 spr 285 TBU spr 625 MAS13 Debug Registers spr 626 MAS23 spr 340 TCR Timer control register spr 627 MAS33 spr 308 DBCR0 Debug control registers 0–3 spr 336 TSR Timer status register spr 628 MAS43 spr 309 DBCR1 spr 630 MAS63 Miscellaneous Registers spr 310 DBCR2 Process ID register 0 spr 561 DBCR3 spr 48 PID0 spr 1008 HID03 Hardware implementation dependent 0–1 spr 1009 HID13 spr 304 DBSR Debug status register MMU Control and Status (Read Only) spr 1013 BUCSR5 Branch control and status register spr 562 DBCNT 5 Debug count register spr 1015 MMUCFG3 MMU configuration spr 272–279 SPRG0–7 General SPRs 0–7 spr 312 IAC1 Instruction address compare registers 1–4 spr 688 TLB0CFG 3 TLB configuration 0/1 spr 313 IAC2 spr 689 TLB1CFG3 Context Control (Read/Write) spr 314 IAC3 Context control register Parallel Signature Unit Registers5 spr 560 CTXCR5 spr 315 IAC4 Data address compare registers 1 and 2 dcr 272 PSCR PS control spr 316 DAC1 dcr 273 PSSR PS status spr 317 DAC2 dcr 274 PSHR PS high dcr 275 PSLR PS low dcr 276 PSCTR PS counter dcr 277 PSUHR PS update high dcr 278 PSULR PS update low |
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