UPD17217GT datasheet(25/84 Pages) NEC

25 / 84 page

µPD17215, 17216, 17217, 17218

3.6

INT Pin

This pin inputs an external interrupt request signal. At either the rising or falling edge of the signal input to this pin, the

IRQ flag (RF: address 3EH, bit 0) is set.

The status of this pin can be read by using the INT flag (RF: address 0FH, bit 0). When the high level is input to the pin,

the INT flag is set to “1”; when the low level is input, the flag is reset to “0” (refer to 7.2.1 INT).

Fig. 3-1

Relations between Port Register and Each Pin

Bank Address

Bit

Port

Output Form

70H

Port 0A

Input only

71H

Port 0B

72H

Port 0C

N-ch

open-drain

(Output only)

73H

Port 0D

b 3

b 2

b 1

b 0

P0A 3

P0A 2

P0A 1

P0A 0

b 3

b 2

b 1

b 0

P0B 3

P0B 2

P0B 1

P0B 0

b 3

b 2

b 1

b 0

P0C 3

P0C 2

P0C 1

P0C 0

b 3

b 2

b 1

b 0

P0D 3

P0D 2

P0D 1

P0D 0

6FH

Port 0E

COMS

push-pull

b 3

b 2

b 1

b 0

P0E 3

P0E 2

P0E 1

P0E 0

Contents to Be Read

Input Mode

Output Mode

Pin status

Output

latch

On Reset

Input mode

(w/pull-up resistor)

Output mode

(Low level output)

Input mode

(w/pull-up resistor)

Contents to Be Written

Input Mode

Output Mode

Output

latch

Output

latch

UPD17217GT Datasheet(PDF) 25 Page - NEC

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