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UPD17217GT Datasheet(PDF) 40 Page - NEC |
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UPD17217GT Datasheet(HTML) 40 Page - NEC |
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40 / 84 page ![]() µPD17215, 17216, 17217, 17218 40 7.2 Hardware of Interrupt Control Circuit This section describes the flags of the interrupt control circuit. (1) Interrupt request flag and interrupt enable flag The interrupt request flag (IRQxxx) is set to 1 when an interrupt request is generated, and is automatically cleared to 0 when the interrupt processing is excuted. An interrupt enable flag (IPxxx) is provided to each interrupt request flag. When the IPxxx flag is 1, the interrupt is enabled; when it is 0, the interrupt is disabled. (2) EI/DI instruction Whether an accepted interrupt is executed or not is specified by the EI or DI instruction. When the EI instruction is executed, INTE (interrupt enable flag), which enables the interrupt, is set to 1. The INTE flag is not registered on the register file. Consequently, the status of this flag cannot be checked by an instruction. The DI flag clears the INTE flag to 0 to disable all the interrupts. The INTE flag is also cleared to 0 at reset, disabling all the interrupts. Table 7-2 Interrupt Request Flags and Interrupt Enable Flag Interrupt Signal Setting Interrupt Request Flag Interrupt Request Flag Enable Flag IRQTM Reset by 8-bit timer. IPTM IRQ Set when edge of INT pin input signal is detected IP IRQBTM Reset by basic interval timer. IPBTM |
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