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UPD17217GT Datasheet(PDF) 44 Page - NEC |
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UPD17217GT Datasheet(HTML) 44 Page - NEC |
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44 / 84 page  µPD17215, 17216, 17217, 17218 44 7.3 Interrupt Sequence If IRQxxx flag is set to “1” when IPxxx flag is “1”, interrupt processing is started after the instruction cycle of the instruction executed when IRQxxx flag was set has ended. Since the MOVT instruction, EI instruction, and the instruction which matches the condition to skip use two instruction cycles, the interrupt enabled while this instruction is executed is processed after the second instruction cycle is over. If IPxxx flag is “0”, the interrupt processing is not performed even if IRQxxx flag is set, until IPxx flag is set. If two or more interrupts are enabled simultaneously, the interrupts are processed starting from the one with the highest priority. The interrupt with the lower priority is kept pending until the processing of the interrupt with the higher priority is finished. 7.3.1 Operations when interrupt is accepted When an interrupt has been accepted, the CPU performs processing in the following sequence: Clears IRQ corresponding to INTE flag and accepted interrupt ××× Decrements value of stack pointer by 1 (SP-1) Saves contents of program counter to stack addressed by stack pointer Loads vector address to program counter Save contents of PSWORD to interrupt stack register One instruction cycle is required to perform the above processing. |
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