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UPD17217GT Datasheet(PDF) 41 Page - NEC |
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UPD17217GT Datasheet(HTML) 41 Page - NEC |
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41 / 84 page ![]() µPD17215, 17216, 17217, 17218 41 7.2.1 INT This flag reads the INT pin status. When a high level is input to the INT pin, this flag is set to “1”; when a low level is input, the flag is reset to “0”. 32 10 0 0 0 INT Address RF : 0FH INT On reset Undefined R/W R 0 1 INT Pin Level Detection INT pin : Low level INT pin : High level 7.2.2 IEG This pin selects the interrupt edge to be detected on the INT pin. When this flag is “0”, the interrupt is detected at the rising edge; when it is “1”, the interrupt is detected at the falling edge. 32 10 0 0 0 IEG Address RF : 1FH IEG On reset 0H R/W R/W 0 1 INT Pin Interrupt Detection Edge Selection Rising edge of INT pin Falling edge of INT pin |
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