LC87FBG08A

No.A2046-14/30

Allowable Operating Conditions

at Ta = -40

°C to +85°C, VSS1 = 0V

Parameter

Symbol

Pin/Remarks

Conditions

Specification

VDD[V]

min

typ

max

unit

Operating

supply voltage

(Note 2-1)

VDD(1)

VDD1

0.245

μs ≤ tCYC ≤ 200μs

2.7

5.5

V

VDD(2)

0.294

μs ≤ tCYC ≤ 200μs

2.2

5.5

VDD(3)

0.735

μs ≤ tCYC ≤ 200μs

1.8

5.5

Memory

sustaining

supply voltage

VHD

VDD1

RAM and register contents sustained

in HOLD mode.

1.6

High level

input voltage

VIH(1)

Ports 1, 2, 7

1.8 to 5.5

0.3VDD+0.7

VDD

VIH(2)

Ports 0

1.8 to 5.5

0.3VDD+0.7

VDD

VIH(3)

CF1, CF2, RES

1.8 to 5.5

0.75VDD

VDD

Low level

input voltage

VIL(1)

Ports 1, 2, 7

4.0 to 5.5

VSS

0.1VDD+0.4

1.8 to 4.0

VSS

0.2VDD

VIL(2)

Ports 0

4.0 to 5.5

VSS

0.15VDD+0.4

1.8 to 4.0

VSS

0.2VDD

VIL(3)

CF1, CF2, RES

1.8 to 5.5

VSS

0.25VDD

High level

output current

IOH(1)

Ports 0, 1, 2

Per 1 applicable pin

4.5 to 5.5

-1.0

mA

IOH(2)

2.7 to 4.5

-0.35

IOH(3)

1.8 to 2.7

-0.15

IOH(4)

P05 (System clock

output function

used)

Per 1 applicable pin

4.5 to 5.5

-6.0

IOH(5)

2.7 to 4.5

-1.4

IOH(6)

1.8 to 2.7

-0.8

IOH(1)

Ports 0, 1, 2

Total of all applicable pins

4.5 to 5.5

-25

IOH(2)

2.7 to 4.5

-8.0

IOH(3)

1.8 to 2.7

-3.5

Low level

output current

IOL(1)

Ports 0, 1, 2

Per 1 applicable pin

4.5 to 5.5

7

IOL(2)

2.7 to 4.5

1

IOL(3)

1.8 to 2.7

0.5

IOL(4)

P70, CF2

Per 1 applicable pin

2.7 to 5.5

1

IOL(5)

1.8 to 2.7

0.5

IOL(6)

P00, P01

Per 1 applicable pin

4.5 to 5.5

15

IOL(7)

2.7 to 4.5

2

IOL(8)

1.8 to 2.7

1

IOL(1)

Ports 0

Total of all applicable pins

4.5 to 5.5

40

IOL(2)

2.7 to 4.5

10

IOL(3)

1.8 to 2.7

5

IOL(4)

Ports 0, 1, 2, CF2

Total of all applicable pins

4.5 to 5.5

70

IOL(5)

2.7 to 4.5

21

IOL(6)

1.8 to 2.7

10.5

IOL(7)

Ports 7

Total of all applicable pins

2.7 to 5.5

1

IOL(8)

1.8 to 2.7

0.5

Instruction

cycle time

(Note 2-2)

tCYC

2.7 to 5.5

0.245

200

μs

2.2 to 5.5

0.294

200

1.8 to 5.5

0.735

200

External

system clock

frequency

FEXCF

CF1

• CF2 pin open

• System clock frequency division

ratio=1/1

• External system clock duty=50±5%

2.7 to 5.5

0.1

12

MHz

1.8 to 5.5

0.1

4

• CF2 pin open

• System clock frequency division

ratio=1/2

• External system clock duty=50±5%

3.0 to 5.5

0.2

24.4

2.0 to 5.5

0.2

8

Note 2-1: VDD must be held greater than or equal to 2.2V in the flash ROM onboard programming mode.

Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a

division ratio of 1/2.

Continued on next page.