AX8052F151 datasheet(46/51 Pages) ONSEMI

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Application Information

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AX8052F151

every VDDA and VDD_IO pin. In order to reduce noise on the antenna inputs it is recommended to

add 27 pF on the VDD pins close to the antenna interface.

The AX8052F151 has an integrated voltage regulator for the analog supply voltages, which

generates a stable supply voltage VREG from the voltage applied at VDD_IO. Use VREG to supply

all the VDDA supply pins and also to DC power to the pins ANTP and ANTN.

7.1. Antenna Interface Circuitry

The ANTP and ANTN pins provide RF input to the LNA when AX8052F151 is in receiving mode,

and RF output from the PA when AX8052F151 is in transmitting mode. A small antenna can be

connected with an optional translation network. The network must provide DC power to the PA

and LNA. A biasing to VREG is necessary.

Beside biasing and impedance matching, the proposed networks also provide low pass filtering to

limit spurious emission.

Single-Ended Antenna Interface

Optional filter

stage to suppress

TX harmonics

CC1

CB1

LT2

Ω single-

ended

equipment

or antenna

IC Antenna

Pins

VREG

LT1

LC2

LC1

CM1

LB1

CB2

LB2

CF1

CF2

LF1

CT1

CT2

CC2

CM2

Figure 10 Structure of the antenna interface to 50 Ω single-ended equipment or antenna

Frequency

Band

LC1,2

[nH]

CC1,2

[pF]

LT1,2

[nH]

CT1,2

[pF]

CM1,2

[pF]

LB1,2

[nH]

CB1,2

[pF]

LF1

[nH]

CF1,2

[pF]

868 / 915

MHz

0.9

2.4

2.7

0 OHM

N.C.

433 MHz

120

2.2

7.5

6.0

5.2

0 OHM

N.C

AX8052F151 Datasheet(PDF) 46 Page - ON Semiconductor

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