AX8052F151 datasheet(44/51 Pages) ONSEMI

44 / 51 page

Transceiver

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AX8052F151

6.11. Voltage Regulator

The AX8052F151 transceiver uses its own dedicated on-chip voltage regulator to create a stable

supply voltage for the transceiver circuitry at pin VREG from the primary supply VDD_IO. All VDDA

pins of the device must be connected to VREG. The antenna pins ANTP and ANTN must be DC

biased to VREG. The I/O level of the digital pins is VDD_IO.

The voltage regulator requires a 1μF low ESR capacitor at pin VREG.

In power-down mode the voltage regulator typically outputs 1.7 V at VREG, if it is powered-up its

output rises to typically 2.5 V. At device power-up the regulator is in power-down mode.

The voltage regulator must be powered-up before receive or transmit operations can be initiated.

This is handled automatically when programming the device modes via the

AX5051_PWRMODE

VREG contains status bits that can be read to check if the regulated voltage is above 1.3

V or 2.3 V, sticky versions of the bits are provided that can be used to detect low power events

(brown-out detection).

AX8052F151 Datasheet(PDF) 44 Page - ON Semiconductor