AX8052F151 datasheet(34/51 Pages) ONSEMI

34 / 51 page

Circuit Description

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AX8052F151

5.11. Ports

VDDIO

PORTx.y

DIRx.y

Special Function

PALTx.y

PINx read clock

PINx.y

Interrupt

INTCHGx.y

ANALOGx.y

65 kΩ

Figure 8 Port pin schematic

Figure 8 shows the GPIO logic. The DIR register bit determines whether the port pin acts as an

output (1) or an input (0).

If configured as an output, the PALT register bit determines whether the port pin is connected to a

peripheral output (1), or used as a GPIO pin (0). In the latter case, the PORT register bit

determines the port pin drive value.

If configured as an input, the PORT register bit determines whether a pull-up resistor is enabled

(1) or disabled (0). Inputs have schmitt-trigger characteristic. Port A inputs may be disabled by

setting the ANALOGA register bit; this prevents additional current consumption if the voltage level

of the port pin is mid-way between logic low and logic high, when the pin is used as an analog

input.

Port A, B and C pins may interrupt the microcontroller if their level changes. The INTCHG register

bit enables the interrupt. The PIN register bit reflects the value of the port pin. Reading the PIN

AX8052F151 Datasheet(PDF) 34 Page - ON Semiconductor