LAN8820 datasheet(30/83 Pages) MICROCHIP

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LAN8820/LAN8820I

DS00001871B-page 30

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3.9.6

LOOPBACK OPERATION

The local loopback mode is enabled by setting the Loopback bit of the Basic Control Register. In this mode, the scram-

bled transmit data (output of the scrambler) is looped into the receive logic (input of the descrambler). This mode is use-

ful as a board diagnostic and serves as a quick functional verification of the device.

3.9.7

IEEE 1149.1 (JTAG) BOUNDARY SCAN

The device includes an integrated JTAG boundary-scan test port for board-level testing. The interface consists of four

pins (TDO, TDI, TCK and TMS) and includes a state machine, data register array, and an instruction register. The JTAG

pins are described in Table 2-5, "JTAG Pins". The JTAG interface conforms to the IEEE Standard 1149.1 - 1990 Stan-

dard Test Access Port (TAP) and Boundary-Scan Architecture

All input and output data is synchronous to the TCK test clock input. TAP input signals TMS and TDI are clocked into

the test logic on the rising edge of TCK, while the output signal TDO is clocked on the falling edge.

The JTAG logic is reset via a hardware reset or when the TMS and TDI pins are high for five TCK periods.

The implemented IEEE 1149.1 instructions and their op codes are shown in Table 3-11.

3.9.8

ADVANCED FEATURES

The device implements several advanced features to enhance manageability of the Ethernet link. These features are

detailed in the following sub-sections.

3.9.8.1

Crossover Indicators

The device reports crossed channels in the XOVER Resolution 0:1 and XOVER Resolution 2:3 fields of the User Status

2 Register. This feature is useful for trouble-shooting problems during network installation.

3.9.8.2

Polarity Inversion Indicators

The device automatically detects and corrects inverted signal polarity. This is reported in the polarity inversion bits

(POLARITY_INV_3, POLARITY_INV_2, POLARITY_INV_1 and POLARITY_INV_0) of the User Status 1 Register.

The polarity inversion bit for Channel 1 (POLARITY_INV_1) is valid after auto-negotiation is complete as indicated by

the Auto-Negotiate Complete bit of the Basic Status Register. The polarity inversion bits for Channels 0, 2 and 3

(POLARITY_INV_0, POLARITY_INV_2, POLARITY_INV_3) are valid only after the link is up as indicated by the Link

Status bit of the Basic Status Register.

Note:

During transmission in local loopback mode, nothing is transmitted to the line and the transmitters are pow-

ered down.

TABLE 3-11:

IEEE 1149.1 OP CODES

INSTRUCTION

OP CODE

COMMENT

Bypass

111

Mandatory Instruction

Sample/Preload

010

Mandatory Instruction

EXTEST

000

Mandatory Instruction

Clamp

011

Optional Instruction

HIGHZ

100

Optional Instruction

IDCODE

001

Optional Instruction

Note:

All digital I/O pins support IEEE 1149.1 operation. Analog pins and the XO pin do not support IEEE 1149.1

operation.

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