LAN8820 datasheet(34/83 Pages) MICROCHIP

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LAN8820/LAN8820I

DS00001871B-page 34

 2009-2015 Microchip Technology Inc.

4.0

This chapter describes the various control and status registers (CSR’s). All registers follow the IEEE 802.3 (clause

22.2.4) management register set. All functionality and bit definitions comply with these standards. The IEEE 802.3 spec-

ified register index (in decimal) is included with each register definition, allowing for addressing of these registers via

the Serial Management Interface (SMI) protocol.

The device registers are categorized into following groups:

• Primary PHY Registers

• Advanced PHY Registers

4.1

Table 4-1 describes the register bit attributes used throughout this document.

Many of these register bit notations can be combined. Some examples of this are shown below:

• R/W: Can be written. Will return current setting on a read.

• R/WAC: Will return current setting on a read. Writing anything clears the bit.

TABLE 4-1:

Notation

Read:

A register or bit with this attribute can be read.

Write:

A register or bit with this attribute can be written.

Read only:

Read only. Writes have no effect.

Write only:

If a register or bit is write-only, reads will return unspecified data.

Write One to Clear:

writing a one clears the value. Writing a zero has no effect.

WAC

Write Anything to Clear:

writing anything clears the value.

Read to Clear:

Contents is cleared after the read. Writes have no effect.

Latch Low:

Clear on read of register.

Latch High:

Clear on read of register.

Self-Clearing:

Contents is self-cleared after the being set. Writes of zero have no effect.

Contents can be read.

RO/LH

Read Only, Latch High:

This mode is used by the Ethernet PHY registers. Bits with this

attribute will stay high until the bit is read. After it a read, the bit will remain high, but will

change to low if the condition that caused the bit to go high is removed. If the bit has not

been read the bit will remain high regardless of if its cause has been removed.

NASR

Not Affected by Software Reset:

The state of NASR bits does not change on assertion

of a software reset.

Either a 1 or 0.

RESERVED

Reserved Field:

Reserved fields must be written with zeros, unless otherwise indicated,

to ensure future compatibility. The value of reserved bits is not guaranteed on a read.

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