LAN8820 datasheet(69/83 Pages) MICROCHIP

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DS00001871B-page 69

LAN8820/LAN8820I

5.5.5

RGMII TIMING

This section specifies the RGMII interface transmit and receive timing. The RGMII interface supports the independent

enabling/disabling of the PHY TXC and RXC delays, each with unique timing properties. These timing are reflected in

the following sub-sections. Please refer to Section 3.3, "RGMII Interface," on page 18 for additional details.

5.5.5.1

PHY TXC Delay Enabled Timing

Note 5-1

7.2ns for 1000BASE-T operation, 36ns for 100BASE-TX operation, 360ns for 10BASE-T operation.

Minimum limits are non-sustainable long term.

Note 5-2

8ns for 1000BASE-T operation, 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.

Note 5-3

8.8ns for 1000BASE-T operation, 44ns for 100BASE-TX operation, 440ns for 10BASE-T operation.

Maximum limits are non-sustainable long term.

Note 5-4

45% for 1000BASE-T operation, 40% for 100BASE-TX or 10BASE-T operation.

Note 5-5

55% for 1000BASE-T operation, 60% for 100BASE-TX or 10BASE-T operation.

Note:

All RGMII timing specifications assume a point-to-point test circuit as defined in Figure 3 of the RGMII spec-

ification 1.3.

FIGURE 5-5:

RGMII PHY TXC DELAY ENABLED TIMING

TABLE 5-14:

RGMII PHY TXC DELAY ENABLED TIMING VALUES

Symbol

Description

Min

Typ

Max

Units

ttxc

TXC period

Note 5-1

Note 5-2

Note 5-3

tclkh

TXC high time

Note 5-4

Note 5-5

tclkl

TXC low time

Note 5-4

Note 5-5

tsetup

TXD[3:0], TXCTRL setup time to edge of TXC

-0.9

thold

TXD[3:0], TXCTRL hold time after edge of TXC

2.7

TXC

TXD[3:0]

TXCTRL

tclkh

tclkl

ttxc

TXD

[3:0]

TXD

[7:4]

TXEN

TXER

thold

tsetup

thold

tsetup

thold

tsetup

thold

tsetup

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