C165 datasheet(62/77 Pages) INFINEON

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C165

Data Sheet

V2.0, 2000-12

AC Characteristics

Demultiplexed Bus (Reduced Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2

tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

ALE high time

11 +

–TCL - 14

–ns

Address setup to ALE

5 +

–TCL - 20

–ns

ALE falling edge to RD,

WR (with RW-delay)

15 +

–TCL - 10

–ns

ALE falling edge to RD,

WR (no RW-delay)

- 10 +

tA –- 10

–ns

RD, WR low time

(with RW-delay)

t12 CC 34 + tC

–2TCL - 16

–ns

RD, WR low time

(no RW-delay)

t13 CC 59 + tC

–3TCL - 16

–ns

RD to valid data in

(with RW-delay)

t14 SR –

22 +

–2TCL - 28

RD to valid data in

(no RW-delay)

t15 SR –

47 +

–3TCL - 28

ALE low to valid data in

t16 SR –

45 +

tA + tC

–3TCL - 30

tA + tC

Address to valid data in

t17 SR –

57 +

tA + tC

–4TCL - 43

+ 2

tA + tC

Data hold after RD

rising edge

t18 SR 0

–

Data float after RD rising

edge (with RW-delay1))

t20 SR –

36 +

tA + tF

–2TCL - 14

+ 22

Data float after RD rising

edge (no RW-delay1))

t21 SR –

15 +

tA + tF

–TCL - 10

+ 22

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