C165 datasheet(13/77 Pages) INFINEON

13 / 77 page

C165

Data Sheet

V2.0, 2000-12

RSTIN

I/O

Reset Input with Schmitt-Trigger characteristics. A

low level at this pin while the oscillator is running

resets the C165. An internal pullup resistor permits

power-on reset using only a capacitor connected to

VSS. A spike filter suppresses input pulses < 10 ns.

Input pulses >100 ns safely pass the filter. The

minimum duration for a safe recognition should be

100 ns + 2 CPU clock cycles.

In bidirectional reset mode (enabled by setting bit

BDRSTEN in register SYSCON) the RSTIN line is

internally pulled low for the duration of the internal

reset sequence upon any reset (HW, SW, WDT).

See note below this table.

Note: To let the reset configuration of PORT0 settle

a reset duration of ca. 1 ms is recommended.

RST

OUT

Internal Reset Indication Output. This pin is set to a

low level when the part is executing either a

hardware-, a software- or a watchdog timer reset.

RSTOUT remains low until the EINIT (end of

initialization) instruction is executed.

NMI

Non-Maskable Interrupt Input. A high to low

transition at this pin causes the CPU to vector to the

NMI trap routine. When the PWRDN (power down)

instruction is executed, the NMI pin must be low in

order to force the C165 to go into power down mode.

If NMI is high, when PWRDN is executed, the part

will continue to run in normal mode.

If not used, pin NMI should be pulled high externally.

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin Nr

TQFP

Pin Nr

MQFP

Input

Outp.

Function

C165 Datasheet(PDF) 13 Page - Infineon Technologies AG

C165 Datasheet(HTML) 13 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL