C165 datasheet(63/77 Pages) INFINEON

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C165

Data Sheet

V2.0, 2000-12

Data valid to WR

t22 CC 24 + tC

–2TCL - 26

–ns

Data hold after WR

t24 CC 15 + tF

–TCL - 10

–ns

ALE rising edge after

RD, WR

t26 CC - 12 + tF –- 12 + tF

–ns

Address hold after WR2)

t28 CC 0 + tF

–0 +

–ns

ALE falling edge to CS3)

t38 CC - 8 - tA

10 -

-8 -

10 -

CS low to Valid Data In3)

t39 SR –

47 +

tC + 2tA

–3TCL - 28

tC + 2tA

CS hold after RD, WR3)

t41 CC 9 + tF

–TCL - 16

–ns

ALE falling edge to

RdCS, WrCS (with RW-

delay)

t42 CC 19 + tA

–TCL - 6

–ns

ALE falling edge to

RdCS, WrCS (no RW-

delay)

t43 CC - 6 + tA

–- 6

–ns

RdCS to Valid Data In

(with RW-delay)

t46 SR –

20 +

–2TCL - 30

RdCS to Valid Data In

(no RW-delay)

t47 SR –

45 +

–3TCL - 30

RdCS, WrCS Low Time

(with RW-delay)

t48 CC 38 + tC

–2TCL - 12

–ns

RdCS, WrCS Low Time

(no RW-delay)

t49 CC 63 + tC

–3TCL - 12

–ns

Data valid to WrCS

t50 CC 28 + tC

–2TCL - 22

–ns

Data hold after RdCS

t51 SR 0

–

Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2

tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

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