C164SL datasheet(59/79 Pages) INFINEON

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C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

A/D Converter Characteristics

(Operating Conditions apply)

Table 13

A/D Converter Characteristics

Parameter

Symbol

Limit Values

Unit Test

Conditions

min.

max.

Analog reference supply

VAREF SR 4.0

VDD + 0.1 V

1) TUE is tested at V

AREF =5.0 V, VAGND =0 V, VDD = 4.9 V. It is guaranteed by design for all other voltages

within the defined voltage range.

If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V

(i.e.

VAREF = VDD = +0.2 V) the maximum TUE is increased to ±3 LSB. This range is not 100% tested.

The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see

IOV

specification) does not exceed 10 mA.

During the reset calibration sequence the maximum TUE may be

±4 LSB.

Analog reference ground

VAGNDSR VSS - 0.1 VSS + 0.2 V

–

Analog input voltage range

VAIN SR VAGND

VAREF

2) V

AIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in

these cases will be X000H or X3FFH, respectively.

Basic clock frequency

fBC

0.5

6.25

MHz 3)

3) The limit values for f

BC must not be exceeded when selecting the CPU frequency and the ADCTC setting.

Conversion time

CC –

tBC +

tS + 2tCPU

–

tCPU = 1 / fCPU

4) This parameter includes the sample time t

S, the time for determining the digital result and the time to load the

result register with the conversion result.

Values for the basic clock

tBC depend on programming and can be taken from Table 14.

This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

Calibration time after reset

tCAL CC –

3328

tBC

–

5) During the reset calibration conversions can be executed (with the current accuracy). The time required for

these conversions is added to the total reset calibration time.

Total unadjusted error

TUE

CC –

±2LSB 1)

Internal resistance of

reference voltage source

RAREF SR –

tBC / 60

- 0.25

Ω

tBC in [ns]

6)7)

6) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference voltage source must allow the capacitance to reach its respective voltage level

within each conversion step. The maximum internal resistance results from the programmed conversion

timing.

7) Not 100% tested, guaranteed by design and characterization.

Internal resistance of analog

source

RASRC SR –

tS / 450

- 0.25

Ω

tS in [ns]

7)8)

ADC input capacitance

CAIN CC –

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