C164SL datasheet(63/79 Pages) INFINEON

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C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

RD, WR low time

(no RW-delay)

t13 CC 50 + tC

–

3TCL - 10

–

RD to valid data in

(with RW-delay)

t14 SR –

20 +

–

2TCL - 20

RD to valid data in

(no RW-delay)

t15 SR –

40 +

–

3TCL - 20

ALE low to valid data in

t16 SR –

40 +

–

3TCL - 20

tA + tC

Address to valid data in

t17 SR –

50 + 2

–

4TCL - 30

+ 2

tA + tC

Data hold after RD

rising edge

t18 SR 0

–

Data float after RD

t19 SR –

26 +

–

2TCL - 14

Data valid to WR

t22 CC 20 + tC

–

2TCL - 20

–

Data hold after WR

t23 CC 26 + tF

–

2TCL - 14

–

ALE rising edge after RD,

t25 CC 26 + tF

–

2TCL - 14

–

Address hold after RD,

t27 CC 26 + tF

–

2TCL - 14

–

ALE falling edge to CS1)

t38 CC -4 - tA

10 -

-4 -

10 -

CS low to Valid Data In1)

t39 SR –

+ 2

–

3TCL - 20

tC + 2tA

CS hold after RD, WR1)

t40 CC 46 + tF

–

3TCL - 14

–

ALE fall. edge to RdCS,

WrCS (with RW delay)

t42 CC 16 + tA

–

TCL - 4

–

Multiplexed Bus (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2

tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

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