C164SL datasheet(69/79 Pages) INFINEON

69 / 79 page

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

AC Characteristics

Demultiplexed Bus

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2

tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

ALE high time

10 +

–

TCL - 10

–

Address setup to ALE

4 +

–

TCL - 16

–

ALE falling edge to RD,

WR (with RW-delay)

10 +

–

TCL - 10

–

ALE falling edge to RD,

WR (no RW-delay)

-10 +

tA –

-10

–

RD, WR low time

(with RW-delay)

t12 CC 30 + tC

–

2TCL - 10

–

RD, WR low time

(no RW-delay)

t13 CC 50 + tC

–

3TCL - 10

–

RD to valid data in

(with RW-delay)

t14 SR –

20 +

–

2TCL - 20

RD to valid data in

(no RW-delay)

t15 SR –

40 +

–

3TCL - 20

ALE low to valid data in

t16 SR –

40 +

tA + tC

–

3TCL - 20

tA + tC

Address to valid data in

t17 SR –

50 +

tA + tC

–

4TCL - 30

+ 2

tA + tC

Data hold after RD

rising edge

t18 SR 0

–

Data float after RD rising

edge (with RW-delay1))

t20 SR –

26 +

tA + tF

–

2TCL - 14

+ 22

Data float after RD rising

edge (no RW-delay1))

t21 SR –

10 +

tA + tF

–

TCL - 10

+ 22

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