C164SL datasheet(76/79 Pages) INFINEON

76 / 79 page

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

AC Characteristics

Figure 24

CLKOUT Timing

Notes

1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

2) The leading edge of the respective command depends on RW-delay.

3) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may

be inserted here.

For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without

MTTC waitstate this delay is zero.

4) The next external bus cycle may start here.

CLKOUT

(Operating Conditions apply)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

CLKOUT cycle time

t29 CC 40

2TCL

CLKOUT high time

t30 CC 14

–

TCL - 6

–

CLKOUT low time

t31 CC 10

–

TCL - 10

–

CLKOUT rise time

t32 CC –

–

4ns

CLKOUT fall time

t33 CC –

–

4ns

CLKOUT rising edge to

ALE falling edge

t34 CC 0 + tA

10 +

0 +

10 +

CLKOUT

ALE

MUX/Tristate 3)

Running cycle1)

Command

RD, WR

C164SL Datasheet(PDF) 76 Page - Infineon Technologies AG

C164SL Datasheet(HTML) 76 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL