C164SL datasheet(70/79 Pages) INFINEON

70 / 79 page

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Data valid to WR

t22 CC 20 + tC

–

2TCL - 20

–

Data hold after WR

t24 CC 10 + tF

–

TCL - 10

–

ALE rising edge after RD,

t26 CC -10 + tF –

-10 +

–

Address hold after WR2)

t28 CC 0 + tF

–

0 +

–

ALE falling edge to CS3)

t38 CC -4 - tA

10 -

-4 -

10 -

CS low to Valid Data In3)

t39 SR –

40 +

tC + 2tA

–

3TCL - 20

tC + 2tA

CS hold after RD, WR3)

t41 CC 6 + tF

–

TCL - 14

–

ALE falling edge to RdCS,

WrCS (with RW-delay)

t42 CC 16 + tA

–

TCL - 4

–

ALE falling edge to RdCS,

WrCS (no RW-delay)

t43 CC -4 + tA

–

-4

–

RdCS to Valid Data In

(with RW-delay)

t46 SR –

16 +

–

2TCL - 24

RdCS to Valid Data In

(no RW-delay)

t47 SR –

36 +

–

3TCL - 24

RdCS, WrCS Low Time

(with RW-delay)

t48 CC 30 + tC

–

2TCL - 10

–

RdCS, WrCS Low Time

(no RW-delay)

t49 CC 50 + tC

–

3TCL - 10

–

Data valid to WrCS

t50 CC 26 + tC

–

2TCL - 14

–

Data hold after RdCS

t51 SR 0

–

Data float after RdCS

(with RW-delay)1)

t53 SR –

20 +

–

2TCL - 20

+ 2

tA + tF

Demultiplexed Bus (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2

tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

C164SL Datasheet(PDF) 70 Page - Infineon Technologies AG

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