C164SL datasheet(15/79 Pages) INFINEON

15 / 79 page

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Functional Description

The architecture of the C164CI combines advantages of both RISC and CISC

processors and of advanced peripheral subsystems in a very well-balanced way. In

addition the on-chip memory blocks allow the design of compact systems with maximum

performance.

The following block diagram gives an overview of the different on-chip components and

of the advanced, high bandwidth internal bus structure of the C164CI.

Note: All time specifications refer to a CPU clock of 25 MHz

(see definition in the AC Characteristics section).

Figure 3

Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are

connected to the CPU via separate buses. A fourth bus, the XBUS, connects external

resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3).

The XBUS resources (XRAM, CAN) of the C164CI can be enabled or disabled during

initialization by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules

that are disabled consume neither address space nor port pins.

C166-Core

CPU

Interrupt Bus

XTAL

MCB04323_4ci

Osc / PLL

RTC

WDT

Interrupt Controller 16-Level

Priority

PEC

External Instr. / Data

GPT1

SSC

BRGen

(SPI)

ASC0

BRGen

(USART)

ADC

10-Bit

Channels

CCOM2

CCOM6

T12

T13

EBC

XBUS Control

External Bus

Control

IRAM

Internal

RAM

2 KByte

ProgMem

ROM: 48/64

OTP: 64

KByte

Data

CAN

Rev 2.0B active

Instr. / Data

Port 0

XRAM

2 KByte

Port 5

Port 3

Port 8

Peripheral Data Bus

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