C164SL datasheet(24/79 Pages) INFINEON

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C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

The Capture/Compare Unit CAPCOM2

The general purpose CAPCOM2 unit supports generation and control of timing

sequences on up to 8 channels with a maximum resolution of 16 TCL. The CAPCOM

units are typically used to handle high speed I/O tasks such as pulse and waveform

generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software

timing, or time recording relative to external events.

Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for

the capture/compare register array.

Each dual purpose capture/compare register, which may be individually allocated to

either CAPCOM timer and programmed for capture or compare function, has one port

pin associated with it which serves as an input pin for triggering the capture function, or

as an output pin to indicate the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the current

contents of the allocated timer will be latched (‘capture’d) into the capture/compare

generated. Either a positive, a negative, or both a positive and a negative external signal

transition at the pin can be selected as the triggering event. The contents of all registers

which have been selected for one of the five compare modes are continuously compared

with the contents of the allocated timers. When a match occurs between the timer value

and the value in a capture/compare register, specific actions will be taken based on the

selected compare mode.

Table 5

Compare Modes (CAPCOM2)

Compare Modes

Function

Mode 0

Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1

Pin toggles on each compare match;

several compare events per timer period are possible

Mode 2

Interrupt-only compare mode;

only one compare interrupt per timer period is generated

Mode 3

Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;

only one compare event per timer period is generated

Double

Two registers operate on one pin; pin toggles on each compare

match;

several compare events per timer period are possible.

Registers CC16 & CC24

Registers CC17 & CC25

Registers CC18 & CC26

Registers CC19 & CC27

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