C164SL datasheet(62/79 Pages) INFINEON

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C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx

registers and represent the special characteristics of the programmed memory cycle.

The following table describes, how these variables are to be computed.

Note: Please respect the maximum operating frequency of the respective derivative.

AC Characteristics

Table 15

Memory Cycle Variables

Description

Symbol

Values

ALE Extension

TCL

× <ALECTL>

Memory Cycle Time Waitstates

2TCL

× (15 - <MCTC>)

Memory Tristate Time

2TCL

× (1 - <MTTC>)

Multiplexed Bus

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2

tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

ALE high time

10 +

–

TCL - 10

–

Address setup to ALE

4 +

–

TCL - 16

–

Address hold after ALE

10 +

–

TCL - 10

–

ALE falling edge to RD,

WR (with RW-delay)

10 +

–

TCL - 10

–

ALE falling edge to RD,

WR (no RW-delay)

-10 +

tA –

-10 +

–

Address float after RD,

WR (with RW-delay)

t10 CC –

–

6ns

Address float after RD,

WR (no RW-delay)

t11 CC –

–

TCL + 6

RD, WR low time

(with RW-delay)

t12 CC 30 + tC

–

2TCL - 10

–

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