C164SL datasheet(71/79 Pages) INFINEON

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C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Data float after RdCS

(no RW-delay)1)

t68 SR –

0 +

–

TCL - 20

+ 2

tA + tF

Address hold after

RdCS, WrCS

t55 CC -6 + tF

–

-6 +

–

Data hold after WrCS

t57 CC 6 + tF

–

TCL - 14 +

–

1) RW-delay and t

A refer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.

Therefore address changes before the end of RD have no impact on read cycles.

3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Demultiplexed Bus (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2

tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

C164SL Datasheet(PDF) 71 Page - Infineon Technologies AG

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