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Z80 Datasheet(PDF) 81 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 81 Page - Zilog, Inc. |
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81 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access BAI Bus Acknowledge In (input, active Low). Signals that the system buses have been released for DMA control. BAO Bus Acknowledge Out (output, active Low). In multiple-DMA configura- tions, this pin signals that the CPU has relinquished control of the bus. BAI and BAO form a daisy-chain for multiple DMA priority resolution over bus control. Unlike the interrupt daisy-chain formed with the IEI and IEO lines, this chain does not allow preemption of control by a high-priority DMA when a lower-priority DMA is already bus master. The DMA that has the bus is always allowed to finish, regardless of its priority in the chain. BUSREQ Bus Request (bidirectional, active Low, open-drain). As an output, this pin sends requests for control of the system address bus, data bus, and control bus to the CPU. As an input when multiple DMAs are strung together in a priority daisy-chain through BAI and BAO, this pin senses when another DMA has requested the buses and causes this DMA to delay its bus request until the first DMA is finished. Because this bidirectional pin allows simul- taneous bidirectional signals with no means of control, no buffers come between this DMA and other DMAs. There can, however, be buffers between it and the CPU because it is unidirectional into the CPU. A 1.8 Kohms pull-up resistor is typically connected to this pin. CE/WAIT Chip Enable and Wait (input, active Low). Normally, this functions only as aCE line, but it can also be programmed to serve as a WAIT function. As a CE line from the CPU, this pin becomes active when IORQ is active and the I/O port address (up to 16 bits) on the system address bus is the DMA’s address, thereby allowing control bytes to be written from the CPU to the DMA. As a WAIT line from memory or I/O devices, after the DMA has received a bus acknowledge (BUSACK) from the CPU, this pin causes wait |
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