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Z80 Datasheet(PDF) 61 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 61 Page - Zilog, Inc. |
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61 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access DMA FUNCTIONAL DESCRIPTION Features • Single Highly Versatile Channel • Dual Port Address Generation with Incrementing, Decrementing, or Fixed Address in Both Ports • Buffered Address and Block-Length Registers • 64 Kbyte Maximum Block Length • 2.4 or 4 MHz Clock Rates (Z80 or Z80A DMA) • 1.25 or 2 MB/s Data Rate (Z80 or Z80A DMA) • Transfer, Search, or Transfer/Search Operations • Bit-Maskable Byte Searching • Sequential (Flow-Through) or Simultaneous (Flyby) Transfers • Compatible with Z80 and Many Other CPUs • Byte, Burst, and Continuous Modes • Auto Restart Capability • Variable Cycle Timing • Wait-Line Cycle Extension • Internally Modifiable Interrupt Vectors • Programmable Interrupts on Ready, End-of-Block, Byte Match • Hardware Priority Daisy-Chains for Bus Requests and Interrupts • Periodic Pulse Generation for External Device • 21 Writeable Control Registers • Seven Readable Status Registers |
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