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Z80 Datasheet(PDF) 32 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 32 Page - Zilog, Inc. |
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32 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Counter/Timer Channels IORQ Input/Output Request from CPU (input, active Low). The IORQ signal is used in conjunction with the CE and RD signals to transfer data and channel control words between the Z80 CPU and the CTC. During a CTC Write cycle, IORQ and CE must be true and RD false. The CTC does not receive a specific write signal. Instead it generates one internally from the inverse of a valid RD signal. In a CTC Read cycle, IORQ,CE,and RD must be active to place the contents of the down-counter on the Z80 data bus. If IORQ and M1 are both true, the CPU is acknowledging an interrupt request, and the highest priority interrupting channel places its interrupt vector on the Z80 data bus. RD Read Cycle Status from the CPU (input, active Low). The RD signal is used in conjunction with the IORQ and CE signals to transfer data and channel control words between the Z80 CPU and the CTC. During a CTC Write Cycle, IORQ and CE must be true and RD false. The CTC does not receive a specific write signal, instead it generates one internally from the inverse of a valid RD signal. In a CTC Read cycle, IORQ CE,and RD must be active to place the contents of the down-counter on the Z80 data bus. IEI Interrupt Enable In (input, active High). This signal is used to form a system-wide interrupt daisy-chain which establishes priorities when more than one peripheral device in the system has interrupting capability. A High level on this pin indicates that no other interrupting devices of higher priority in the daisy chain are being serviced by the Z80 CPU. IEO Interrupt Enable Out (output, active High. The IEO signal, in conjunction with IEI, is used to form a system-wide interrupt priority daisy-chain. IEO is High only if IEI is High and the CPU is not servicing |
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