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Z80 Datasheet(PDF) 30 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 30 Page - Zilog, Inc. |
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30 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Counter/Timer Channels Figure 7. 44-Pin Quad Flat Pack Pin Assignments Bit 7–Bit 0 System Data Bus (bidirectional, tristate). This busisused totransfer all date and command words between the Z80 CPU and the Z80 CTC. There are eight bits on this bus, of which bit 0 is the least-significant. CSI CSO Channel Select (input, active High). These pins form a 2-bit binary address code for selecting one of the four independent CTC channels for an I/O WriteorRead. (SeeTable 4). 34 33 N/C CS1 CLK/TRG3 CLK/TRG2 N/C N/C CLK/TRG1 CLK/TRG0 N/C +5V N/C IEO IORQ N/C ZC/TO2 ZC/TO1 N/C ZC/TO0 N/C RD GND D7 44 22 12 11 1 CMOS Z80 CTC |
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