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Z80 Datasheet(PDF) 97 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 97 Page - Zilog, Inc. |
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97 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Bus Request Daisy-Chains Multiple DMAs can be linked in a prioritized daisy-chain for the purpose of requesting the bus. Figure 31 illustrates this procedure. Each DMA’s BUSREQ pin is bidirectional. As an output, it requests the bus. As an input, this pin senses when another DMA in the daisy-chain has requested the bus (brought the BUSREQ line Low) and therefore prevents this DMA from also requesting the bus until the other DMA has finished. Any DMA that has the bus is always allowed to finish its operation; a higher priority DMA cannot preempt it during this time. Their proximity to the CPU determines the priority of DMAs in a daisy- chain. The DMA electrically closest to the CPU (as measured along the BUSACKI/BAI lines) has the highest priority. Priority matters only when multiple DMAs request the bus on the same clock cycle. The higher priority DMA can then prevent lower priority DMAs from receiving a bus- acknowledge signal through the BAI/BAO chain. The lower priority DMAs continue to hold their BUSREQ lines Low until the higher priority DMA finishes and releases the bus, thereby allowing lower priority DMAs to contend for the bus. Figure 31. Bus-Requesting Daisy-Chain 1.8K CPU BUSREQ BUSACK DMA BAI BAO BUSREQ DMA BAI BAO BUSREQ |
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