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Z80 Datasheet(PDF) 43 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 43 Page - Zilog, Inc. |
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43 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Counter/Timer Channels Figure 9. CTC Write Cycle CTC Read Cycle Figure 10 illustrates the timing associated with the CTC Read cycle. This sequence is used when CPU reads the current contents of the down counter. During clock cycle T2, the Z80 CPU initiates the Read cycle with true signals at input pins RD (Read), IORQ (I/O Request), and CE (Chip Enable). A 2-bit binary code appears at CTC inputs CS1 and CS0 (Channel Select 1 and 0), specifying which of the four CTC channels is being read from. (See Note below.) On the rising edge of the cycle T3, the valid contents of the down-counter rising edge of cycle T2 is available on the Z80 data bus. No additional wait states are allowed. M1 must be false to distinguish the cycle from an interrupt acknowledge. CS0. CS1, CE IORQ RD M1 Channel Address T1 T1 T2 TWA T3 Note: |
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