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Z80 Datasheet(PDF) 96 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 96 Page - Zilog, Inc. |
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96 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access When the DMA has requested and received the bus from the CPU, other devices on the system do not perceive the change. The CPU is idle during this time because it cannot fetch instructions from memory. Bus Requesting Two conditions enable the DMA to request the bus from the CPU: an enabling command from the CPU, and an active Ready condition, resulting from either an active Ready line from an I/O device or a Force Ready command by the CPU. The DMA requests the bus by latching its BUSREQ line Low. The CPU always responds to a bus request and it does so quickly, in no more than one machine cycle (3 to 10 clock cycles) plus one additional clock cycle by lowering its BUSACK line as an input to the DMA’s BAI line. Both the DMA’s BUSREQ output and the CPU’s BUSACK output remain Low whilethe DMA has thebus. The bus is released back to the CPU when the DMA’s BUSREQ line goes High; the CPU’s BUSACK line goes High in the next clock cycle. The DMA releases its BUSREQ line in a variety of conditions, including: • Completion of single-byte transfer (Byte mode • Ready line going inactive (Byte and Burst modes) • Byte match (Burst and Continuous modes) if stop-on-match is programmed • End-of-block (all modes), if stop-on-end-of-block is programmed These conditions are explained in the “Timing” chapter. Bus requests cannot be made while the CPU services an interrupt from the DMA. This is prevented by the Interrupt Under Service (IUS) latch, which is discussed later. |
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