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Z80 Datasheet(PDF) 94 Page - Zilog, Inc.

Part # Z80
Description  Z80 CPU PERIPHERALS
PDF  330 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z80 Datasheet(HTML) 94 Page - Zilog, Inc.

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UM008101-0601
Direct Memory Access

Notes
:
* Address can increment (+) or decrement (-) from the programmed starting address (As), which is the first
address for transfer purposes.
** Occurs only in 2-cycle (variable timing) simultaneous transfers when the Ready line is still active at the end
of the N + 1 byte transfer.
*** Simultaneous transfers cannot have both ports variable. This class of operation is programmed as a DMA
search-only operation, with variable addresses ascribed to the programmed source port. What the DMA senses
is the source port may be either the real source or destination, as determined by external hardware. See “The
actual number of bytes transferred is one more than specified by the block length.
* These entries are
necessary only in the case of a fixed destination address.” on page 129.
Table 11. Contents of Counters After DMA Stops Because of End-of-Block (Transfer
Operations)
Class
Mode
Programmed
Block Length
Bytes Transferred
At Stop
Byte Counter
Source Port
Address Counter*
Destination Port
Address Counter*
Sequential
Byte
N
N+1
N
As
±(N+1)
As
±(N)
Transfer
Burst
N
N+1
N
As
±(N+1)
As
±(N)
Continuous
N
N+1
N
As
±(N+1)
As
±(N)
Search Only or
Simultaneous
Transfer/Search
Byte
N
N+1
N
As
±(N+1)
***
Burst
N
N+1
N+1
As
±(N+1)
***
Burst
N
N+2**
N+1 **
As
±(N+2)**
***
Continuous
N+1
N+1
N+1
As
±(N+1)
***
Continuous
N+1
N+2**
N+1 **
As
±(N+2)**
***
Table 12. Contents of Counters After DMA Stops Due to Byte Match (Search or Transfer/
Search Operations)
Class
Mode
Match Occurs
On This Byte
Bytes Transferred At Stop
If Transferring
Byte Counter
Source Port
Address Counter*
Destination Port
Address Counter
Sequential
Transfer
Byte
M
M
M-1
As
±(M)
As
±(M-1)
Burst
M
M
M-1
As
±(M)
As
±(M-)
Continuous
M
M+
M-1
As
±(M)
As
±(M -)
Search Only or
Simultaneous
Transfer Search
Byte
MM
MAs
±(M)
***
Burst
M
M+1
M+1
As
±(M+1)
***
Burst
M
M**
M-1**
As
±(M**
***
Continuous
M
M+1
M+1
As
±(M+1)
***



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