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Z80 Datasheet(PDF) 36 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 36 Page - Zilog, Inc. |
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36 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Counter/Timer Channels Timing may be initialized automatically or with a triggering edge at the channel’s Timer Trigger (CLK/TRG) input. This timing is determined by programming bit 3 of the channel control word. If bit 3 is reset?, the timer automatically begins operation at the start of the CPU cycle following the I/ O Write machine cycle that loads the time constant data word to the channel. If bit 3 is set, the timer begins operation on the second succeeding rising edge of Φ after the Timer Trigger edge following the loading of the time constant data word. If no time constant word is to follow, the timer begins operation on the second succeeding rising edge of Φ after the Timer Trigger edge and following the control word write cycle. Bit 4 of the channel control word is pre programmed to select whether the Timer Trigger is sensitive to a rising or falling edge. There is no setup requirement between the active edge of the Timer Trigger and the next rising edge of Φ. If the Timer Trigger edge occurs closer than a specified minimum setup time to the rising edge of Φ, the down-counter does not begin decrementing until the following rising edge of Φ. If bit 7 in the channel control word is set, the zero-count condition in the down-counter causes a pulse at the channel’s Time Out pin, and initiates an interrupt request sequence. (For more details, see “CTC Interrupt Servicing” on page 27). CTC PROGRAMMING Overview To begin counting or timing operations, a Channel Control Word and Time Constant Data Word are written to the appropriate channel by the CPU. These words are stored in the Channel Control or Time Constant registers of each channel. If a channel has been programmed to enable interrupts, an interrupt vector is written to the appropriate register in the CTC. Because of |
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