Z80 datasheet(228/330 Pages) ZILOG

228 / 330 page

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7UGT /CPWCN

UM008101-0601

Serial Input/Output

208

• TTL-Compatible Inputs and Outputs

• Two Independent Full-Duplex Channels

• Data Rates in Synchronous or Isosynchronous Modes:

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0-800K Bits/Second with 4 MHz System Clock Rate

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0-1.2M Bits/Second with 6 MHz System Clock Rate

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0-2.5M Bits/Second with 10 MHz System Clock Rate

• Receiver Data Registers Quadruply Buffered; Transmitter Doubly

Buffered

• Asynchronous Features:

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5, 6, 7, or 8 Bits per Character

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1, 1 1/2, or 2 Stop Bits

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Even, Odd, or No Parity

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x1, x16, x32, and x64 Clock Modes

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Break Generation and Detection

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Parity, Overrun, and Framing Error Detection

• Binary Synchronous Features:

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Internal or External Character Synchronization

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One or Two Sync Characters in Separate Registers

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Automatic Sync Character Insertion

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CRC Generation and Checking

• HDLC and IBM SDLC Features:

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Abort Sequence Generation and Detection

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Automatic Zero Insertion and Deletion

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Automatic Flag insertion Between Messages

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Address Field Recognition

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1-Field Residue Handling

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Valid Receive Messages Protected from Overrun

Z80 Datasheet(PDF) 228 Page - Zilog, Inc.

Z80 Datasheet(HTML) 228 Page - Zilog, Inc.

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