DP83865 datasheet(46/86 Pages) NSC

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3.0 Configuration (Continued)

3.10.1 MII/GMII Interface

The link speed is determined by Auto-Negotiation, by

strapping options, or by register writes. Based on the

speed linked, an appropriate MAC interface is enabled.

3.10.2 RGMII Interface

The

Reduced

Gigabit

Media

Independent

Interface

(RGMII) is a proposed standard by HP and 3Com. RGMII

is an alternative data interface to GMII and MII. RGMII

reduces the MAC interface pin count to 12.

The RGMII can be enabled either through strapping option

or MDIO register write. The strapping pins are shared with

CRS/RGMII_SEL0 and TX_CLK/RGMII_SEL1 since CRS

and TX_CLK signals are not used in the RGMII mode.

To enable RGMII through software, Register AUX_CTL

0x12.13:12 should be “10” or “11” binary. Note that

enabling the RGMII interface disables GMII and MII inter-

faces.

3.11 Clock to MAC Enable

The DP83865 has a clock output (pin 85) that can be used

as a reference clock for other devices such as MAC or

switch silicon. The Clock to MAC output can be enabled

through strapping pins.

The Clock to MAC Enable Strap (pin 88) enables the clock

output. The output frequency can be selected between 25

MHz or 125 MHz. The frequency selection strapping pin is

combined with COL (pin 39), CLK_MAC_FRQ.

Note that upon power up, the clock output is available after

GPHY goes through its internal reset and initialization pro-

cess. The clock output can be interrupted when GPHY is

going through software reset.

3.12 MII/GMII/RGMII Isolate Mode

The DP83865 can be placed into MII/GMII/RGMII Isolate

mode by writing to bit 10 of the BMCR 0x00.

3.12.1 10/100 Mbps Isolate Mode

In Isolation Mode, the DP83865 does not respond to

packet data present at TXD[3:0], TX_EN, and TX_ER

inputs and presents a high impedance on the TX_CLK,

RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS out-

puts. The DP83865 will continue to respond to all manage-

ment transactions through MDIO.

While in Isolate mode, all medium access operations are

disabled.

3.12.2 1000 Mbps Isolate Mode

During 1000 Mbps operation, the isolate mode will TRI-

STATE the GMII outputs of the GigPHYTER V. The PHY

also enters into the power down mode. All medium access

operations are halted. The only way to communicate to the

PHY is through MDIO management port.

3.13 Loopback Mode

The DP83865 includes a Loopback Test mode for easy

board diagnostics. The Loopback mode is selected through

bit 14 (Loopback) of BMCR 0x00. Writing 1 to this bit

enables MII/GMII transmit data to be routed to the MII/GMII

receive outputs. While in Loopback mode the data will not

be transmitted onto the media. This is true for 10Mbps, 100

Mbps, as well 1000 Mbps data.

In 10BASE-T, 100BASE-TX, 1000BASE-T Loopback mode

the data is routed through the PCS and PMA layers into the

PMD sublayer before it is looped back. Therefore, in addi-

tion to serving as a board diagnostic, this mode serves as

quick functional verification of the device.

3.14 IEEE 802.3ab Test Modes

IEEE 802.3ab specification for 1000BASE-T requires that

the PHY layer be able to generate certain well defined test

patterns on TX outputs. Clause 40 section 40.6.1.1.2 “Test

Modes” describes these tests in detail. There are four test

modes as well as the normal operation mode. These

modes can be selected by writing to the 1KTCR 0x09 as

shown.

Table 42. Auto-Negotiation Disabled

SPEED[1:0]

Link Strapped

Controller I/F

10BASE-T

MII

100BASE-TX

MII

1000BASE-T

GMII/RGMII

reserved

---

Table 43. Auto-Negotiation Enabled

Link Negotiated

Controller I/F

10BASE-T

MII

100BASE-TX

MII

1000BASE-T

GMII/RGMII

Table 44. RGMII Strapping for HP mode

Signal

Strap

CRS/RGMII_SEL0

TX_CLK/RGMII_SEL1

Table 45. RGMII Strapping for 3COM mode

Signal

Strap

CRS/RGMII_SEL0

TX_CLK/RGMII_SEL1

Table 46. IEEE Test Mode Select

bit 15

bit 14

bit 13

Test Mode Selected

= Test Mode 4

= Test Mode 3

= Test Mode 2

= Test Mode 1

= Normal Operation

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