DP83865 datasheet(73/86 Pages) NSC

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6.0 Electrical Specifications (Continued)

6.2 Reset Timing

Parameter

Description

Notes

Min

Typ

Max

Units

Reference clock settle time

The reference clock must be stable af-

ter the last power supply voltage has

settled and before RESET is deas-

serted. (Note 1)

Pins VDD_SEL and CLK_MAC_EN

are latched in during this time.

µs

Hardware RESET Pulse

Width

Power supply voltages and the refer-

ence clock (CLK_IN) have to be sta-

ble.

150

µs

Post RESET Stabilization

time prior to MDC preamble

for register accesses

MDIO is pulled high for 32-bit serial

management initialization.

External pull configuration

latch-in time from the deas-

sertion of RESET

Hardware Configuration Pins are de-

scribed in the Pin Description section.

Reset includes external hardware and

internal software through registers.

(Note 2)

CLK_TO_MAC Output Sta-

bilization Time

If enabled, the CLK_TO_MAC output,

being independent of RESET, power-

down mode and isolation mode, is

available after power-up.

CLK_TO_MAC is a buffered output

CLK_IN. (Note 1)

0 + T1

µs

Note 1: Guaranteed by design. Not tested.

Note 2: It is recommended to use external pull-up and/or pull-down resistors for each of the hardware configuration pins that provide fast RC time con-

stants in order to latch-in the proper value prior to the pin transitioning to an output driver. Unless otherwise noted in the Pin Description section all

external pull-up or pull-down resistors are recommended to be 2k

Ω.

RESET

MDC

32 clocks

Latch-In of Hardware

Configuration Pins

CLK_IN

VDD 1.8V (core, analog),

2.5V (I/O, analog),

3.3V (I/O if applicable)

CLK_TO_MAC

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