DP83865 datasheet(74/86 Pages) NSC

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6.0 Electrical Specifications (Continued)

6.3 Clock Timing

6.4 1000 Mb/s Timing

6.4.1 GMII Transmit Interface Timing

Parameter

Description

Notes

Min

Typ

Max

Units

CLK_IN Duty Cycle

CLK_IN tR/tF

10% to 90%

1.0 to 2.5

CLK_IN frequency

(25 MHz +/-50 ppm)

24.99875

25.000000 25.001250

MHz

CLK_IN

Parameter

Description

Notes

Min

Typ

Max

Units

GTX_CLK Duty Cycle

T10

GTX_CLK tR/tF

Note 1,4,5

T11

Setup from valid TXD, TX_EN and TXER to

↑ GTX_CLK

Note 2,4

2.0

T12

Hold from

↑ GTX_CLK to invalid TXD, TX_EN and TXER

Note 3,4

0.0

T13

GTX_CLK Stability

Note 5

-100

+100

ppm

T14

GMII to MDI latency

152

Note 1: tr and tf are measured from VIL_AC(MAX) = 0.7V to VIH_AC(MIN) = 1.9V.

Note 2: tsetup is measured from data level of 1.9V to clock level of 0.7V for data = ‘1’; and data level = 0.7V to.clock level 0.7V for data = ‘0’.

Note 3: thold is measured from clock level of 1.9V to data level of 1.9V for data = ‘1’; and clock level = 1.9V to.data level 0.7V for data = ‘0’.

Note 4: GMII Receiver input template measured with “GMII point-to-point test circuit”, see Test Conditions Section

Note 5: Guaranteed by design. Not tested.

GTX_CLK

T11

T12

T13

T10

TXD[7:0], TX_EN,

TX_ER

T10

Begin of Frame

T14

MDI

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