DP83865 datasheet(13/86 Pages) NSC

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1.0 Pin Description (Continued)

RESERVED

Reserved Reserved: Leave floating.

TCK

Input

JTAG Test Clock: This pin should be left float-

ing if not used.

CORE_VDD

Power

Core VDD: (Digital) Connect to 1.8V.

VSS

Ground

Ground: Connect to common ground plane.

TMS

Input

JTAG Test Mode Select: This pin should be left

floating if not used.

TDO

Output

JTAG Test Data Output: This pin should be left

floating if not used.

IO_VDD

Power

I/O VDD: (Digital) Connect to 2.5V or 3.3V. The

VDD_SEL pin must be tied accordingly.

VSS

Ground

Ground: Connect to common ground plane.

TDI

Input

JTAG Test Data Input: This pin should be left

floating if not used.

TRST

Input

JTAG Test Reset: This pin should be pulled

down through a 2k

Ω resistor if not used.

RESET

Input

Reset: Connect to board reset signal.

VDD_SEL_STRAP

Strap

I/O VDD Select: Pull high to select 3.3V or low

to select 2.5V. The pin must be connected direct-

ly to power or ground (no pull-up/down resistor!).

CORE_VDD

Power

Core VDD: (Digital) Connect to 1.8V.

VSS

Ground

Ground: Connect to common ground plane.

IO_VDD

Power

I/O VDD: (Digital) Connect to 2.5V or 3.3V. The

VDD_SEL pin must be tied accordingly.

VSS

Ground

Ground: Connect to common ground plane.

COL

Output

Collision: Connect to MAC chip through a single

Ω impedance trace. This output is capable of

driving 35 pF load and is not intended to drive

connectors, cables, backplanes or multiple trac-

es. This applies if the part is in 100 Mbps mode

or 1000 Mbps mode.

CRS/RGMII_SEL0

Output

Carrier Sense: Connect to MAC chip through a

single 50

Ω impedance trace. This output is ca-

pable of driving 35 pf load and is not intended to

drive connectors, cables, backplanes or multiple

traces. This applies if the part is in 100 Mbps

mode or 1000 Mbps mode.

RX_ER/RXDV_ER

Output

Receive Error: Connect to MAC chip through a

single 50

Ω impedance trace. This output is ca-

pable of driving 35 pf load and is not intended to

drive connectors, cables, backplanes or multiple

traces. This applies if the part is in 100 Mbps

mode or 1000 Mbps mode.

IO_VDD

Power

I/O VDD: (Digital) Connect to 2.5V or 3.3V. The

VDD_SEL pin must be tied accordingly.

VSS

Ground

Ground: Connect to common ground plane.

RX_DV/RCK

Output

Receive Data Valid: Connect to MAC chip

through a single 50

Ω impedance trace. This out-

put is capable of driving 35 pf load and is not in-

tended to drive connectors, cables, backplanes

or multiple traces. This applies if the part is in

100 Mbps mode or 1000 Mbps mode.

Table 1.

Pin #

Data Sheet Pin Name

Type

Connection / Comment

DP83865 Datasheet(PDF) 13 Page - National Semiconductor (TI)

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